1. Field of the Invention
The invention relates to a delay fault test of a semiconductor integrated circuit (IC). More particularly, the invention relates to generating a test vector, and executing a delay fault test with the test vector.
2. Description of the Related Art
Verification of functions and timing in an IC, and especially logic circuits, is typically performed by simulation. Such simulations often employ test vectors to activate a critical path that has been identified by the timing analysis.
Current verification efforts often result in incomplete testing of an IC, though. Verification often focuses on paths with large signal delays, thus centering only on specific circuit blocks or regions known to have large delays. Also, due to dispersion of size and density in manufacturing of an IC, paths which are assumed at verification of timing during a design stage to easily breach timing may not necessarily become an actual breach path after the IC is actually manufactured. The timing breach, if any, may actually be generated on a different path.
Accordingly, it is desirable to execute the delay fault test on a path which is selected so as to cover a large area of the IC. In particular, it is desirable to develop an apparatus that allows users to designate a specific region of an IC, and that generates a test vector by which the specified region is tested.